A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design
نویسنده
چکیده
A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of low threshold voltage. For the most recent CMOS technologies static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip designers. According to ITRS (International technology road-map for semiconductors), leakage power is becoming a dominant part of total power consumption. To prolong the battery life of portable devices, leakage power reduction is the primary goal. The main objective of this paper is to present the analysis of leakage components, comprehensive study & analysis of leakage components and to present different proposed leakage power reduction techniques.
منابع مشابه
Design and Implementation of Low Leakage SRAM Acrhitectures using CMOS VLSI Circuits in Different Technology Environment
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